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00025 #ifndef _QORE_MACHINE_MACROS_H
00026 #define _QORE_MACHINE_MACROS_H
00027
00028 #define STACK_DIRECTION_DOWN 1
00029
00030 #ifdef __GNUC__
00031 #ifdef __LP64__
00032
00033 #define HAVE_ATOMIC_MACROS
00034 #define HAVE_CHECK_STACK_POS
00035
00036
00037 #define ia64_cmpxchg4_acq(ptr, new, old) ({ \
00038 unsigned long ia64_intri_res; \
00039 asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
00040 asm volatile ("cmpxchg4.acq %0=[%1],%2,ar.ccv": \
00041 "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
00042 (int)ia64_intri_res; \
00043 })
00044
00045 static __inline__ int ia64_atomic_add (int i, volatile int *v) {
00046 int old, vnew;
00047
00048 do {
00049 old = *v;
00050 vnew = old + i;
00051 } while (ia64_cmpxchg4_acq(v, vnew, old) != old);
00052 return vnew;
00053 }
00054
00055 static __inline__ int ia64_atomic_sub (int i, volatile int *v) {
00056 int old, vnew;
00057
00058 do {
00059 old = *v;
00060 vnew = old - i;
00061 } while (ia64_cmpxchg4_acq(v, vnew, old) != old);
00062 return vnew;
00063 }
00064
00065 static inline void atomic_inc(volatile int *a) {
00066 ia64_atomic_add(1, a);
00067 }
00068
00069
00070 static inline int atomic_dec(volatile int *a) {
00071 return !ia64_atomic_sub(1, a);
00072 }
00073
00074 static inline size_t get_stack_pos() {
00075 size_t addr;
00076 asm volatile ("mov %0=sp" : "=r" (addr));
00077 return addr;
00078 }
00079
00080 static inline size_t get_rse_bsp() {
00081 size_t addr;
00082 asm volatile ("mov %0=ar.bsp" : "=r" (addr));
00083 return addr;
00084 }
00085
00086 #endif // #ifdef __LP64__
00087 #endif // #ifdef __GNUC__
00088
00089 #ifdef __HP_aCC
00090 #ifdef __LP64__
00091
00092 #define HAVE_ATOMIC_MACROS
00093 #define HAVE_CHECK_STACK_POS
00094
00095
00096 extern "C" void atomic_inc(int *v);
00097 extern "C" int atomic_dec(int *v);
00098 extern "C" size_t get_stack_pos();
00099 extern "C" size_t get_rse_bsp();
00100
00101 #endif // #ifdef __LP64__
00102 #endif // #ifdef __HP_aCC
00103
00104 #endif // #ifndef _QORE_MACHINE_MACROS_H
00105